LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;

entity addr is 
  
  port (
    A,B: in std_logic_vector(31 downto 0);
    CARRYIN: in std_logic;
    SUM : out std_logic_vector(31 downto 0);
    OVERFLOW: out std_logic);
  
end addr;

architecture STRUCTURAL of addr is

  component addr1Bit
    port (
      A,B,Cin: in std_logic;
      S,Cout: out std_logic);
  end component;
  
  signal carrys, sums: std_logic_vector(31 downto 0);
begin
  I00: addr1Bit port map(A(0), B(0), CARRYIN, sums(0), carrys(0));
  I01: addr1Bit port map(A(1), B(1), carrys(0), sums(1), carrys(1));  
  I02: addr1Bit port map(A(2), B(2), carrys(1), sums(2), carrys(2));
  I03: addr1Bit port map(A(3), B(3), carrys(2), sums(3), carrys(3));  
  I04: addr1Bit port map(A(4), B(4), carrys(3), sums(4), carrys(4));
  I05: addr1Bit port map(A(5), B(5), carrys(4), sums(5), carrys(5));  
  I06: addr1Bit port map(A(6), B(6), carrys(5), sums(6), carrys(6));
  I07: addr1Bit port map(A(7), B(7), carrys(6), sums(7), carrys(7));  
  I08: addr1Bit port map(A(8), B(8), carrys(7), sums(8), carrys(8));
  I09: addr1Bit port map(A(9), B(9), carrys(8), sums(9), carrys(9));  
  I010: addr1Bit port map(A(10), B(10), carrys(9), sums(10), carrys(10));
  I011: addr1Bit port map(A(11), B(11), carrys(10), sums(11), carrys(11));  
  I012: addr1Bit port map(A(12), B(12), carrys(11), sums(12), carrys(12));
  I013: addr1Bit port map(A(13), B(13), carrys(12), sums(13), carrys(13));  
  I014: addr1Bit port map(A(14), B(14), carrys(13), sums(14), carrys(14));
  I015: addr1Bit port map(A(15), B(15), carrys(14), sums(15), carrys(15));
  I016: addr1Bit port map(A(16), B(16), carrys(15), sums(16), carrys(16));
  I017: addr1Bit port map(A(17), B(17), carrys(16), sums(17), carrys(17));
  I018: addr1Bit port map(A(18), B(18), carrys(17), sums(18), carrys(18));
  I019: addr1Bit port map(A(19), B(19), carrys(18), sums(19), carrys(19));
  I020: addr1Bit port map(A(20), B(20), carrys(19), sums(20), carrys(20));
  I021: addr1Bit port map(A(21), B(21), carrys(20), sums(21), carrys(21));
  I022: addr1Bit port map(A(22), B(22), carrys(21), sums(22), carrys(22));
  I023: addr1Bit port map(A(23), B(23), carrys(22), sums(23), carrys(23));
  I024: addr1Bit port map(A(24), B(24), carrys(23), sums(24), carrys(24));
  I025: addr1Bit port map(A(25), B(25), carrys(24), sums(25), carrys(25));
  I026: addr1Bit port map(A(26), B(26), carrys(25), sums(26), carrys(26));
  I027: addr1Bit port map(A(27), B(27), carrys(26), sums(27), carrys(27));
  I028: addr1Bit port map(A(28), B(28), carrys(27), sums(28), carrys(28));
  I029: addr1Bit port map(A(29), B(29), carrys(28), sums(29), carrys(29));
  I030: addr1Bit port map(A(30), B(30), carrys(29), sums(30), carrys(30));
  I031: addr1Bit port map(A(31), B(31), carrys(30), sums(31), carrys(31));


  OVERFLOW <= carrys(31) xor carrys(30);
  SUM <= sums;
  
end STRUCTURAL;
